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Код
1:/CS1 2:/CS2
3:/CS12 4:/SLTSL
5: RSV(N.C) 6:/RFSH
7:/WAIT 8:/INT
9:/M1 10:/BUSDIR
11:/IORQ 12:/MERQ
13:/WR 14:/RD
15:/RESET 16: RSV(N.C)
17: A 9 18: A15
19: A11 20: A10
21: A 7 22: A 6
23: A12 24: A 8
25: A14 26: A13
27: A 1 28: A 0
29: A 3 30: A 2
31: A 5 32: A 4
33: D 1 34: D 0
35: D 3 36: D 2
37: D 5 38: D 4
39: D 7 40: D 6
41: GND 42: CLOCK
43: GND 44: SW1
45: +5V 46: SW2
47: +5V 48: +12V
49: SOUNDIN 50: -12V
Код
1 ROM addresses 4000-7FFF select signal
2 ROM addresses 8000-BFFF select signal
3 ROM addresses 4000-BFFF select signal (for 256k ROM)
4 Slot select signal
5 Reserved signal line - use inhibited
6 Refresh cycle signal
7 CPU's WAIT request signal
8 Interrupt request signal to CPU
9 Signal expressing CPU fetch cycle
10 This signal controls direction of external databus buffer
Cartridges are selected and L level is output from each
cartridge at data transmission time
11 I/O request signal
12 Memory request signal
13 Write timing signal
14 Read timing signal
15 System reset signal
16 Reserved signal line - use inhibited
17-32 Address bus signals
33-40 Data bus signals
41 Signal ground
42 CPU clock 3.579545MHz
43 Signal ground
44,46 For insertion/removal protect
45,47 +5V power source
48 +12V power source
49 Sound input signal (-5bdm)
50 -12V power source