This page lists the known issues in the Nios® II development kit version 5.1 and gives workarounds where appropriate.
Issues are grouped in the following categories:
Nios II Processor Core
Peripherals
Host Platform
Device
Nios II IDE
Building Projects
Debugging Projects
Navigating Projects
Flash Programmer
Download Cables & Debug Hardware
Development Boards
Toolchain (gcc, gdb, etc.)
Target Software
Legacy SDK
SOPC Builder & Quartus II Software
Example Designs
Hardware Simulation
Documentation
For new features in this release, see the separate release notes. For revision history of the Nios II processor core, see the Nios II Processor Revision History chapter in the Nios II Processor Reference Handbook.
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This section lists any issues related to the Nios II processor cores.
There are no known issues.
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This section lists any issues related to the embedded peripherals included with the Quartus II software version 5.1, which might impact Nios II users.
On the SOPC Builder PLL component, you cannot access the pfdena signal through the Avalon control register.
If you enable the pfdena signal on the altpll block, the PLL component configuration GUI allows you to select that you want to access the pfdena signal via the PFDENA bit in the control register. However, the hardware does not support this mode of operation. Software attempting to access the PFDENA bit will not function correctly.
Workaround: You can export the pfdena signal to the top level of the system module, or you can disable the pfdena signal on the altpll. The hardware will support this feature in version 6.0 of the Quartus II software.
If the DEV_CLRn pin on the FPGA input has been assigned (in Quartus® II software) to generate a device-wide reset, and the FPGA is reset while the JTAG UART is active, then the JTAG UART might become unstable.
Workaround: Do not use the DEV_CLRn function on the FPGA. Turn off the Enable device wide reset (DEV_CLRn) setting in Quartus II software.
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This section lists any issues related specifically to the host platform.
There is currently no workaround. This will be addressed in a future version.
If you try to interrupt or terminate a debug session targeting the Nios II instruction set simulator (ISS), you might see an error message "Interrupt Failed or Terminate Failed". This means that the nios2-iss process failed to terminate. The debug session appears to have terminated in the IDE, but the nios2-iss process still remains alive.
Workaround: Open a command shell and kill the nios2-iss process.
There is no Quartus II stand-alone programmer for Linux. As a result, in the Nios II IDE the Quartus II Programmer command on the Tools menu has no effect. The IDE does not automatically launch the programmer when you attempt to download software to a board that does not match the expected hardware image.
Workaround: Launch the Quartus II software to access the Quartus II Programmer.
The SOPC Builder and Nios II SDK shell may become unresponsive if run while the Frisk antivirus software is running.
Workaround: Turn off the Dynamic Virus Checking feature of the Frisk software before running SOPC Builder or the Nios II SDK shell.
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This section lists any device-related issues.
Early shipments of the Nios II Development Kit, Stratix II Edition include an EP2S60 engineering sample (ES) device. Stratix II EP2S60 ES devices have a silicon problem that prevents the use of byte enables on MRAM blocks. Refer to the Stratix II FPGA Family Errata Sheet for details.
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This section lists any issues relating to the Nios II IDE.
The Nios II IDE may not prompt for the workspace at startup.
Workaround: Specify the workspace at the command line using the -data argument. For example:
nios2-ide -data <path to workspace>
If the workspace does not exist, it will be created.
Double-clicking a .o file in the Nios II IDE on Windows might cause the IDE to stop responding. This issue occurs only on systems with a separate installation of Cygwin in addition to Cygwin installed with the Nios II development tools.
Workaround: Ensure that only the cygwin1.dll for the Nios II tools is in the PATH when launching Nios II IDE.
If you create a software project in Nios II IDE version 5.0.1 and then install Nios II version 5.1 and try to import that same project into your workspace, you might get an error "Problem deleting folder Debug".
Workaround: If you get this error, close the Nios II IDE and any other application which has files open from the project in question, then manually delete the project Debug and/or Release directories from the file system. Re-import the project in the Nios II IDE version 5.1.
Nios II IDE Advanced projects created with earlier (pre-5.0) versions of the Nios II IDE call 'make clean all' when the project is built, rather than 'make all'. Also, on the Project menu, clicking Clean for these projects has no effect.
Workaround: To change the behavior of the IDE so that the project invokes make all by default for a build and make clean by default for a clean build, do the following:
- Right click on the project and select Properties.
- Select the C/C++ Make Project page.
- In the Workbench Build Behavior section, change the value for Rebuild (Full Build) to all.
- Turn on Clean and type clean in the corresponding text box.
If you rename components in the SOPC Builder system and then regenerate the SOPC Builder system, Nios II IDE system library projects based on that system will have build errors.
Workaround: After regenerating the SOPC Builder system, create a new system library project for the SOPC Builder system. Alternately, you can delete the system library project from the workspace without deleting the contents from the file system, and then re-import the project, selecting the appropriate SOPC Builder system.
If you enable breakpoint filtering for a thread and later turn off filtering for the thread, the debugger might incorrectly continue to filter the thread.
Workaround: There is no workaround.
An issue in the instruction set simulator (ISS) model of the JTAG UART can cause a console communication error during the RAM test when running the Memory Test software template on the ISS.
Workaround: There is no workaround.
Under some cases the ISS does not ignore uninitialized memory reads, even when Unitialized memory reads is set to Ignore on the ISS Settings tab of the run configuration.
Workaround: There is no workaround.
The Use Step Filters button, just to the right of the Step Return button, is not implemented in Nios II IDE version 5.1.
You might be unable to terminate nios2-gdb-server after setting a watch point in the Nios II IDE debugger and resuming execution past the end of main. You will see an error "Terminate failed". You will not be able to start the debugger again; you will see a message reading "Another application is using the target processor..." in the Console view.
Workaround: Terminate the nios2-gdb-server.exe process using the Windows Task Manager.
Workaround: Change the type of global and static local variables to int, long, or unsigned long before setting watchpoints on them.
The Nios II IDE debugger is unable to step into some low-level C library functions, such as __sflags() which is called from _fopen_r(). (_fopen_r() is called from fopen().) If you try to step into such a function, execution will proceed as if you had indicated the debugger should resume execution.
Workaround: Step over such functions. Or, if execution continues after trying to step in, click Suspend on the Run menu.
If the Include load addresses, Include store addresses and/or Include data values... trace options are enabled during debug, the load and store address and data will not appear at the first breakpoint after starting debugging. They will appear at successive breakpoints.
Workaround: To see load or store addresses and data in the instruction trace prior to main, turn on Break at alt_main() on the Debugger tab for your debug configuration.
Watchpoints do not work in the Nios II IDE when the Use FS2 console window for trace and watchpoint support setting is turned on in the Debugger tab of the Debug configuration. You will see an error message "The execution of program is suspended because of error." with details indicating that hardware watchpoints could not be inserted and deleted.
Workaround: If the FS2 console is open, you must use it to control watchpoints. For details, see the FS2 documentation.
Setting breakpoints on adjacent lines of assembly code might cause the Nios II processor to stop responding to the debugger.
Workaround: When debugging in mixed mode or assembly mode view, separate breakpoints by at least one assembly instruction. This issue does not affect Nios II cores that do not have hardware breakpoints enabled in the JTAG debug module.
When searching through files in the IDE workspace, you may get an error message saying that one or more resources are out of sync with the file system.
Workaround: Right click in the Navigator view and choose Refresh, and then perform the search again.
The C/C++ scanner is used for C/C++ Search, navigation, open declaration and parts of content assist. Due to limitations of the C/C++ Scanner, these features will not work with the following code constructs:
- Kernighan & Ritchie-style C
- Functions that take a function-pointer as an argument
Workaround: If the C/C++ Search fails, use the File Search facility.
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The elf2flash utility supports .elf files up to approximately 24 MBytes in size. The elf2flash utility might fail with error "java.lang.OutOfMemoryError" on files larger than 24 MBytes.
Workaround: You can either lower the number of symbols in your elf file by turning off debug symbols, or specify less initialized data in the application.
Booting the Nios II processor from code stored in an Altera EPCS serial configuration device is not supported with Stratix II devices.
Workaround: For further assistance contact Altera Technical Services at http://mysupport.altera.com.
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This section lists any issues related to download cables and other debug hardware.
Debugging with the following Altera download cables might fail, due to electrical noise-related JTAG communication failures: USB-Blaster™ Rev A, ByteBlaster™, ByteBlasterMV™, ByteBlaster II, and MasterBlaster™ cables.
Currently, the only fully supported cable for downloading, debugging, or communicating with Nios II systems is the USB-Blaster Rev B cable or later. Revision B cables are clearly labeled as Revision B. (Revision A cables have no revision label.)
Workaround: Use a USB-Blaster Rev B cable. Older cables can be used, but they might encounter JTAG communication failures.
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This section lists any issues related to the Nios II compiler toolchain.
gprof sometimes reports incorrect call hierarchy information in the call graph output.
Workaround: There is no workaround.
Breakpoints set in a C++ constructor might not halt the processor due to a widespread GNU GCC, GDB issue. This is not a Nios II IDE-specific issue.
Workaround: You can workaround this issue by moving all of your constructor source code into another class method, called init. Then invoke this method from within the constructor.
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This section lists any issues related to target software.
If neither printf() nor cout is used from main() before tasks are started, cout will not work from a task.
Workaround: Add the following C++ code to the beginning of main():std::ios_base::sync_with_stdio(false);
The HAL CFI Flash driver might not work for Toshiba flash memory that claims to be CFI compliant.
Workaround: In the altera_avalon_cfi_flash_table.c file, change the #define READ_ARRAY_MODE from (alt_u8)0xFF to (alt_u8)0xF0 and rebuild the project.
When you first create a component's inc directory or HAL header file, you might first need to perform a clean build (i.e., rebuild) of existing system library projects for the new files to be detected.
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This section lists issues related to legacy SDK support for the Nios II processor. For additional known issues with the Legacy SDK, refer to the Nios II Embedded Processor Support page. Note that Legacy SDK support will be removed in a future release of the Nios II development tools.
The Nios II legacy SDK does not support new features of the Nios II processor and/or SOPC Builder. As a result, systems with multiple clock domains might not function correctly when the legacy SDK is used. For example, peripherals that the CPU communicates with rely on a timing relationship established by the legacy SDK's nasys_clock_freq definition, found in excalibur.h and excalibur.s. The nr_timer_milliseconds() routine in the legacy SDK uses nasys_clock_freq to start a timer to run for one millisecond. If the timer and CPU are on separate clock domains, the timer period will be incorrect.
The Nios II legacy SDK flow does not include support for the SPI peripheral. Legacy SDK drivers for the SPI peripheral are available on the Nios II Embedded Processor Support page.
The JTAG UART did not exist before the release of the Nios II processor, and therefore the pre-Nios II legacy SDK flow provides no driver for the JTAG UART. The Legacy SDK is not being actively developed, and peripherals developed in the future are unlikely to provide support for the legacy SDK.
If program memory and the Nios II reset address both reside at the bottom of a memory, a reset of the processor might not properly boot from the program memory when using the legacy SDK flow. This results from a slightly different boot procedure between Legacy mode and Nios II IDE mode.
Workaround: Place program memory and the reset address at the base of the RAM in question. Place the exception address near the top of the RAM (at least 0x80 bytes from the end).
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On-chip memories can be initialized during the Quartus II compile for FPGAs, but not for HardCopy® devices. The Quartus II fitter may fail if an on-chip memory specifies an initialization file, and the design is being compiled for a HardCopy device.
Workaround: Turn on the HardCopy Compatible box next to the target board settings at the top of the SOPC Builder System Contents tab.
SOPC Builder does not generate an error if you connect Nios II tightly-coupled instruction and data masters to both ports on a dual-port on-chip memory. However, this configuration is not supported in hardware.
Workaround: Do not connect Nios II tightly-coupled masters to both ports of a dual-port memory.
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This section lists any issues related to Altera development boards.
The top two bytes of the SSRAM data are reversed on the Nios II Development Board, CycloneTM II Edition. The Nios II hardware design examples account for this reversal by swapping the byte enables 2 and 3 lines (C and D on the board schematic) in the top level schematic.
Workaround: Ensure that you have swapped the SSRAM byte enables as illustrated in the example designs when creating new designs. Refer to the Nios II Development Board, Cyclone II Edition Reference Manual for more information.
The Nios II processor version 5.0 and higher includes a CompactFlash controller peripheral suitable for interfacing to Compact Flash cards in True IDE mode on Nios development boards. In order for True IDE mode to operate, compact flash cards require that the ATASEL_N input be driven to ground during power-up.
The CompactFlash controller peripheral includes a configurable power register used to power-cycle CompactFlash cards in Nios II software through a MOSFET on the Nios development boards. However, in certain development boards, power to the CompactFlash card will not turn off completely during this power cycle operation. Because of this, the CompactFlash might not sample the ATASEL_N pin during the power-cycle operation after FPGA configuration when this pin is driven to ground. Instead, the CompactFlash card might sample the ATASEL_N pin when power is first applied to the development board, when I/O are not yet driven by the FPGA (before FPGA configuration).
Workaround: If you encounter errors with CompactFlash when using the Nios development boards, try one of the following workarounds:
- Try a different CompactFlash card. Certain cards are more susceptible to the power-cycling issue than others.
- Modify the Nios development board. This is recommended for users who are familiar and comfortable with board-level modifications. Disconnect pin 9 (ATASEL_N) on the CompactFlash socket on your Nios development board and tie this pin to ground. Note that the CompactFlash socket uses a staggered numbering on the pins (starting from pin 1: 1, 26, 2, 27, ...); refer to the CompactFlash Association specification for right-angle surface-mount connectors for exact specifications on this connector. This modification will permanently enable True-IDE mode operation.
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This section lists any issues related to the example designs included with the Nios II development tools.
If you do not regenerate designs containing the DDR SDRAM Controller in SOPC Builder before recompiling the designs in the Quartus II software, the Quartus II Compiler will generate an error due to invalid library paths.
Workaround: Regenerate the EP2C35 example design in SOPC Builder before recompiling in the Quartus II software to setup the appropriate library paths for the DDR component.
The full_featured design for the Nios Development Board, Cyclone II Edition stores copies boot code from the EPCS serial configuration device, which is a slow memory interface. As a result, the Nios II boot time on this board might be noticeably slow.
Workaround: You can change the Nios II CPU configuration wizard settings in SOPC Builder so that the Nios II CPU boots from faster CFI-compliant flash memory on the board.
There is an error in the memtest.c program that prevents it from successfully testing flash memory when the flash memory is full.
Workaround: Erase the flash memory and run the memory test again.
If you are running a networking example design and you are asked for a 9-digit number after the letters 'ASJ', and your Nios II development board does not have a sticker with a 9-digit number after the letters 'ASJ', please enter a unique 9-digit number when prompted. Ensure that this number is unique to each Nios board connected to your network to avoid network address conflicts.
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This section lists issues related to simulating Nios II processor systems on an RTL simulator, such as the ModelSim® simulator.
Running ModelSim RTL simulation of a Nios II system fails if the reset address of the Nios II processor is set to an EPCS Serial Flash Controller.
Workaround: To simulate your system, temporarily set the Reset Address of the Nios II CPU to the memory that your application code will reside (for example, SDRAM), then re-generate the system in SOPC Builder and run RTL simulation again. Before booting the Nios II CPU from EPCS flash on your target board, change the Nios II Reset Address back to the EPCS Controller peripheral and re-generate the system in SOPC Builder and re-compile in Quartus to produce an updated FPGA configuration file in which the Nios II CPU will boot from EPCS flash.
If your program reads the value of an uninitialized BSS variable during HDL simulation when the HAL system library has been compiled with the 'ModelSim only, no hardware support' property enabled in Nios II IDE, a warning will be produced about unfiltered data being ‘x’. This occurs because when this property is enabled, the code that clears the BSS memory region is omitted to speed up HDL simulation so this memory region is uninitialized. The BSS region contains global and static local variables that are not initialized by the application so they default to a value of zero. When the Nios II CPU reads uninitialized variables, it displays a warning and converts any of the bits of the uninitialized data to zero which correctly mimics the effect of the missing BSS clearing code. The HAL code that executes before and after main() may use BSS variables so these warnings might be generated even if your application doesn’t use the BSS.
If you did not enable the simulation option in SOPC Builder when generating the system, and attempt Run As > Nios II ModelSim in the Nios II IDE, you will get an error stating that you there are no simulation files. This might also generate a benign error stating "No printer selected" if your host system has no printers enabled.
Workaround: To successfully simulate your design, enable the simulation option in SOPC Builder, regenerate, and perform the Run As > Nios II ModelSim in the IDE again.
The ModelSim tool might fail to load simulation models for memory arrays larger than 128M bytes, halfwords or words in size. If the sum of the following parameters is greater than 27, the ModelSim tool will fail to load:
- address_bits (i.e. 14)
- column bits (i.e. 11)
- log2(number of banks) (number of banks is usually 4, so this term is usually 2)
- log2(chipselects) (number of chipselects is usually 1, so this term is usually 0)
Workaround: Simulate using a smaller SDRAM than the SDRAM implemented in hardware. This is possible if the entire memory space doesn’t need to be simulated.
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The UART chapter of the Peripherals Handbook incorrectly states:
"When parity is Even, the parity bit is 1 if the character has an even number of 1 bits; otherwise the parity bit is 0. Similarly, when parity is Odd, the parity bit is 1 if the character has an odd number of 1 bits."
This should read:
"When parity is Even, the parity bit is 1 if the number of 1's in the character plus the parity bit is even; otherwise the parity bit is 0. Or in other words, the Parity bit is set to '0' when there is an even number of '1' bits in the character. Similarly, when parity is Odd, the parity bit is 1 if the number of 1's in the character plus the parity bit has an odd number of 1 bits. Or in other words, the Parity bit is set to '0' when there is an odd number of '1' bits in the character."
To display the help content, your computer must able to recognize itself on the network. Incorrect proxy settings can cause the help content to fail to display.
Workaround: Specify valid browser proxy settings.
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