Контроллер Ide для Q-bus, Charles H. Dickman Опции

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Q22-Bus - ATA Disk Adapter
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Project Status January 2004 Lets say this project is not dead, just very dormant. I had the fortune to come upon a QBus SCSI controller and a QBus DSSI controller and so the priority dropped considerably. I think the original design is still viable even without the addition of DMA, etc. April 2002 No progress. A disk crash set me back, losing my latest driver source. Excuses, excuses..... March 2002 Lack of time prevents me from building a prototype based on the new DMA design. February 2002 A volunteer worked on the NetBSD driver for the EIDE Adapter. 11 January 2002 Got a copy of the chipkit users manual which describes the LSI-11 Bus Interface Chips and Accessories. 10 January 2002 Made some updates to the web page. Since I posted to various lists and newsgroups, I have received quite a bit of attention. Thanks to all the comments and suggestions. 1 January 2002 Posted description of project to NetBSD/vax mailing list. Many interesting responses. Project Background I have been reading discussions about Qbus to IDE disk adapters for some time. The only published attempt that I know of was from the Ukraine and was based on SSI- and MSI-TTL and some Russian components. (View it here.) Having reviewed what was available, this is my own attempt... Design of a Q22-Bus - ATA Disk Adapter The Q22-Bus is an asynchronous, open-collector system bus, used for memory and I/O on DEC microPDP-11 processors and I/O on some VAX processors. ATA means AT Attachment and the IDE disk interface is basically an extension of the IBM PC/AT ISA bus, at least for ATA-2. Later revisions introduce features to enhance speed that are generally of no use to the Qbus. The adapter design is simple and obvious: a buffer between the two buses with the control logic necessary to satisfy both sides. Several National DS8838 Bus Transceivers attach directly to the Q22-Bus BDAL lines. Each transceiver section has 3 ports: a bus port connected to the Q22-Bus, a gatable input port connected to adapter Bus B, and an output port connected to adapter Bus A. Two 74ALS244 Tri-State Buffers join adapter Bus A to tri-state adapter Bus B, effectively gating the Q22-Bus BDAL lines to adapter Bus B. The transceivers and tri-state buffers taken together form a interface between the open-collector Q22-Bus and the tri-state adapter Bus B. Two signals, QBRL and QBWL, control the direction. Bus B is connected to the IDE drive data lines and to an Atmel ATF1508 CPLD which implements the bus protocol logic. Additional Q22-Bus and IDE drive control signals are connected to the CPLD through transceivers or directly. A block diagram is found at the top of this file. From the programmers point of view, the adapter and drive appear as a 32-byte block in the Qbus I/O page. I chose address 17771000 because the Ukranian design used it. It is probably not the best. The DMA related registers and the reserved address space respond as memory, but does nothing more. Address Name Direction Size Description 17771000 WD_CSR R/W word Adapter Control Register 17771002 WD_ADDR R/W word DMA Address Register 17771004 WD_COUNT R/W word DMA Count Register 17771006 WD_VECTOR R/W word Interrupt Vector Register 17771010 (r/w) word (reserved) 17771012 (r/w) word (reserved) 17771014 WD_ALTSTS R byte Alternate Disk Status Register WD_CTLR W byte Disk Control Register 17771016 (r/w) word (reserved) 17771020 WD_DATA R/W word Disk Data Register 17771022 WD_ERROR R byte Disk Error Register WD_PRECOMP W byte Disk Precompensation/Feature Register 17771024 WD_SECCNT R/W byte Sector Count Register 17771026 WD_SECTOR R/W byte Sector Register 17771030 WD_CYL_LO R/W byte Low Byte of Cylinder Register 17771032 WD_CYL_HI R/W byte High Byte of Cylinder Register 17771034 WD_SDH R/W byte Disk and Head Select Register 17771036 WD_COMMAND W byte Disk Command Register WD_STATUS R byte Disk Status Register The base address is fixed in the CPLD at 17771000. This was for simplicity and a set of base address select jumpers is planned for. The interrupt vector is programmable through software. Software My primary goal was to have a disk capable of storing a reasonable Unix system. Starting with the 4.3BSD wd disk driver, a 2.11BSD driver slowly developed. Not much of the original code survives, and a better starting point would have been the 2.11BSD RA driver. The driver only supports disks capable of LBA addressing. This was an arbitrary limitation that will likely be eliminated as development continues. Only one drive has been tested, but there is no reason that two drives could not be made to work. Construction The Q Bus like most of the older DEC buses is based on a 0.125 inch spaced card-edge connector. This spacing is a bit unusual and prototype boards are long out of stock. In a PDP8/e project, I sacrificed some M113 Flip Chip modules to the cause, but that seemed wasteful. Therefore, the adapter was constructed not as a board within a chassis, but as a separate "chassis". Two 50-pin IDC headers were wired as if they were an M9405 Q22 mirror image cable connector. This got the board out in the open and available for probing and debugging. This explains all the resistors. The end of the Qbus must be properly terminated. Nothing in the design assumes this, so it could easily be built on a card with the standard DEC connector. Prototype construction was done using a solder pad per hole perf board and point to point wiring. I like to use #30AWG wire with Kynar insulation stripped and soldered at each end. This technique has proven to be very reliable and fairly efficient for construction. Take a tour of the board. PIO vs DMA Traditionally, PDP-11 disk controllers have used direct memory access (DMA) for disk I/O. The Qbus places the burden for DMA on the device controller card. Once the device has negotiated control of the bus, it is responsible for all aspects of the bus protocol. By contrast, IBM PC compatible disk controllers usually transfered data using programmed I/O (PIO), moving each byte (or word) through the processor one at a time, under program control. I have plans for DMA, but they have not been tested. Besides, the PIO performance is very good in comparison with an MSCP SCSI drive. Some discussion indicates that the MSCP controller that I tested against is not the fastest. IDE vs SCSI I have received several comments questioning my selection of IDE over SCSI. The simple answer is the IDE is simple and SCSI is COMPLEX. This may be a personal bias, I don't know a whole lot about SCSI. The second answer is that I have several IDE drives of various sizes, and NO SCSI drives. Finally, VERY large IDE drives are now unbelievably cheap. How long before 1GB = $US1? Not very long I think. One counter argument is that the cable length is quite short for IDE drives. The specs indicate a length of 18 inches maximum. The IDE specs also comment that this restriction is in part based on a fear that the cable and drive will be improperly installed and that they should still perform acceptably, so it may be possible to extend this is applied properly. The Qbus is also quite slow in comparison to the faster modes of the IDE bus. The IDE bus may be settled by the time the Qbus needs it. The point is that many of the objections to IDE may be engineered away when applied to the Qbus. Engineering Package The following is a crude summary of the design. I don't think it is complete. If anyone is really interested in more information, just ask. Block Diagram Schematic CPLD description file 2.11BSD device driver, header file and man page EEPROM boot for the KDJ11-B processor References ATA-2 Specification ATA-3 Specification Annex C contains of discussion of signal integrity in the drive cable. Q22 Specification - part 1, part 2, part 3, and part 4 DEC chipkit users manual LSI-11 Bus Interface Chips and Accessories (Thanks to Carl Lowenstein and Eric Smith.) <!-- Documentation I Wish I Had These materials would have been useful and enlightening. If anyone has them, I would be willing to make copies and make them generally available at my own expense. --> How Fast is it? - I/O Performance I compared the performance of the PIO EIDE disk adapter with a MSCP SCSI controller (CMD CQD-220). The system was a KDJ11-B processor with 2MW of QBus memory (no PMI, not sure if the memory is capable of block mode DMA or not). The test consisted of reading 8000k using dd and dumping the results to /dev/null. This was repeated for block sizes of 512 to 8k, doubling the size at each test. For single sector reads and writes, the EIDE adapter was faster. I attribute this to MSCP overhead. For file system block sized reads and writes, the performance was about equal. For large transfers the EIDE adapter maxed out at about 250kbytes per sec. Measured Performance (kBps) Controller Xfer Size Real System MSCP 512 53.8 101.7 1k 100.5 204.1 2k 179.4 394.1 4k 284.7 720.7 8k 457.1 1379.3 WD 512 58.0 110.0 1k 95.4 177.8 2k 140.4 349.3 4k 181.8 672.3 8k 211.6 1333.3 A real world comparison was made measuring the time to compile the same kernel on each of the devices. Kernel Compile Time Device Duration (mm:ss) MSCP 57:05 WD 36:22 The WD device compiled the kernel in 70% of the time required for the MSCP device. Lots of variables here though. The SCSI drive is about twice as old as the EIDE drive and the on disk buffer much smaller. The important consideration is that the EIDE adapter is not excessively limited because it operates in a PIO mode instead of DMA. Several people have commented on these metrics. The CQD-220 is probably not the fastest competitor, some have experienced higher performance with CQD-440 for example. The KDJ11-B processor, even in a 2 instruction loop that is presumably in cache, only uses about 30% of the QBus bandwidth. This thing could potentially be a whole lot faster.

Images of the adapter board Q22 ATA Adapter - Component Side Q22 ATA Adapter - Solder Side

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